A PSRAM using a DRAM as a basic configuration thereof has been widely used, on behalf of a conventional SRAM, in a device such as a cellular phone wherein low consumption current and large volumes of memory (32 Mb to 128 Mb) are required. In a PSRAM, an increase in speed as well as low current consumption at the time of stand-by and activation (operation) have recently become important elements along with an improvement in functions and performances of a device to be used. For example, in an asynchronous system for an SRAM-compliant interface, a page mode with a cycle time of 15 ns to 20 ns has been introduced, and further, with the aim of further increase in speed, a synchronous system such as a SDRAM has, in general, begun to be adopted. In this synchronous system, writing and reading according to a burst mode for 8 or 16 words are performed with clocks of 75 MHz to 100 MHz or more.
Meanwhile, according to a requirement of a device in use, there is, in a writing system, a single write system in which only one word is written, in addition to the burst mode. By switching a programmable mode register or the like, either the burst write or the single write is selected depending on an operation of a device. Since the single write system writes only one word, the operation thereof is basically unfit for an increase in speed. In case of reading, since the burst mode with 8 or 16 words is the only system to be used, the velocity of a single write is considerably slower than that of a burst read.
Further, the more important point is that once entering into a single write mode, there is a large loss of time for switching to and from a read mode. The result is that an access cycle time including the single write of a memory grows longer. Moreover, even if an increase in speed can be achieved by using a burst read with a long number of word, in case of combining the burst read with a single write, an average data rate on data input/output becomes much lower than a maximum data rate (theoretical value) to be determined by multiplying clock frequency by a data bus width.
FIG. 1 is a schematic view showing a brief description of reading and writing operations in a conventional typical synchronous PSRAM. In FIG. 1, read latency is set as 5 clock cycles, and write latency is set as 4 clock cycles. A CLK represents a clock and a CMD represents an access command signal. A CMD-R and a CMD-W represent a read command and a write command, respectively. With a low CMD, either a reading or writing operation starts. An ATC stands for an “Array Time Constant” and means a series of memory array activation processes from decode of an address being downloaded together with the CMD clock to an increase in potential of a word line, on operation (driving) of a sense amplifier, re-reading, off operation of the word line, off operation of the sense amplifier, and pre-charge for a bit line. Data I/O represents a data input and output.
There is also an alternative write enable (WE) signal, not depicted in FIG. 1. When the CMD is low, if the WE is simultaneously high, a reading operation starts, and if the WE is low, a writing operation starts. In addition, in FIG. 1, any address is not depicted either, however, an address is downloaded together with the CMD clock and an access to a cell specified by the address is performed. The first CMD-R1 is for reading and is decoded after the address being downloaded together with the CMD-R1 passed through an address bus. Thereafter, an array is activated and 8-word burst data comes up on the data I/O from the fifth clock at CMD-R1.
In FIG. 1, for reading data, it is assumed to use a Prefetch system for burst read. After the sense amplifier is turned on, a burst data with 8 words per an I/O is temporarily stored in a latching circuit (not being illustrated) that is one of peripheral circuits from a memory cell through a bit switch (not being illustrated). Therefore, since a memory array can be pre-charged right after data is prefetched, the ATC can be completed in a fairly short amount of time. In a typical PSRAM, the next access command is entered into the second clock from the last data for burst read. In FIG. 1, the CMD-W1 for writing of a single write is inserted at this timing. After the same period of time as that for reading, the memory array is activated from the CMD-W1 during the ATC-W1. The write data being entered in the data I/O at the fourth clock from the CMD-W1 is written into the memory cell.
FIG. 1 illustrates operations wherein the similar reading and writing are repeated below. In the data I/O, the data is used in series only at the time of the burst, however, the data is discontinued due to switching between reading and writing operations. One cycle required for a set of reading and writing (single write) takes 21 clocks, however, 9 clocks of the data I/O are only used. Therefore, the usage rate of the data I/O is only 43% ( 9/21). Hence, an average data rate on the data I/O of a cycle is also only 43% that is a theoretical maximum value. As stated above, in a normal PSRAM, there is a large decrease in a data rate in reading and writing operations including a single write mode.
Related prior art documents include, for example, Japanese Unexamined Patent Publication (Kokai) No. 3362775. This publication discloses an art for improving a data transfer rate of a DRAM. However, the invention being disclosed in this publication targets a burst access in case that reading and writing have the same burst length and a low address changes, and is not an invention for enabling to improve a cycle time and a data rate in various access cycles including a single write.